The Workshop on Design and Architectures for Signal and Image Processing
(DASIP) provides an inspiring international forum for the latest
innovations and developments in the field of leading signal, image and
video processing and machine learning in custom embedded, edge and cloud
computing architectures and systems. The workshop program will include
keynote speeches and contributed paper sessions. The 19th edition will
be held in conjunction with the 21th HiPEAC Conference in Krakow,
Poland, January 26-28, 2026.

IMPORTANT DATES (ALL 23:59 A.O.E)

Preliminary cycle:
Abstract submission deadline: September 15, 2025
Paper submission deadline: September 19, 2025
Notification and feedback: October 24, 2025

Main cycle:
Abstract submission deadline: November 10, 2025
Paper submission deadline: November  17th, 2025
Notification of acceptance: December 19th, 2025
Camera ready papers: January 17th, 2026
Workshop: January 26-28, 2026

VENUE

The Workshop on Design and Architectures for Signal and Image Processing
will be held in conjunction with the 21th HiPEAC Conference in Krakow,
Poland, January 26-28, 2026.

REGISTRATION

DASIP 2026 is a HiPEAC-based workshop. Hence, a registration at HiPEAC
is required. Please be aware that for each accepted paper, at least, one
of the authors must pay the full registration fee in order for the paper
to be included in the workshop proceedings and scheduled in the program.

SUBMISSION GUIDELINES

Authors should submit their full papers (up to 12 pages) in the
single-column Springer LNCS format in PDF through the HotCRP system.
Submitted papers are required to describe original unpublished work and
must not be under consideration for publication elsewhere. Submissions
must be fully anonymous, but authors should not hide previous work,
instead, they need to make self-references in the third person. More
details on submission requirements, templates, and submission
instructions are provided on the DASIP website.

The submission process is in two cycles: the preliminary one, and the
main one. Submitting to the preliminary cycle is not mandatory. Only the
main cycle is decisive. However, authors submitting to the preliminary
cycle will either receive an early acceptance notice and thus will be
exempted from the main cycle, or a rejection accompanied by reviews.
Those reviews can then be used to enhance the paper and submit it again
during the main cycle. Thus, submitting to the preliminary cycle is advised.
Each submission will receive at least three independent double-blind
reviews from the members of our scientific committee. Authors are
encouraged to take the reviewers’ comments into account when they
prepare the final versions of their papers and present the research
during the workshop before its publication. The conference proceedings
will be published in the Springer LNCS Series, on the Springer Link
website. Paper and keynote presentation slides and tutorial documents
will be made available to workshop attendees after the workshop (subject
to confidentiality issues).

CONTACT

All questions about the workshop and submissions should be emailed to
Marcin Kowalczyk <kowalczyk@agh.edu.pl> or Camille Monière
<camille.moniere@univ-ubs.fr>.

LIST OF TOPICS

Prospective authors are invited to submit manuscripts on topics
including, but not limited to:

Custom embedded, edge and cloud architectures and systems:
Machine learning and deep learning architectures for inference and training
Systems for autonomous vehicles : cars, drones, ships and space applications
Image processing and compression architectures
Smart cameras, security systems, behaviour recognition
Edge and cloud processing: special routing, configurable co-processors
and low energy considerations
Real-time cryptography, secure computing, financial and personal data
processing
Computer arithmetic, approximate computing, probabilistic computing,
nanocomputing, bio-inspired computing
Biological data collection and analysis, bioinformatics
Personal digital assistants, natural language processing, wearable
computing and implantable devices
Global navigation satellite and inertial navigation systems

Design Methods and Tools:
Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
High-level synthesis, logic synthesis, communication synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics

Development Platforms, Architectures and Technologies:
Embedded platforms for multimedia and telecommunication
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Memory system and cache management
Asynchronous (self-timed) circuits and analog and mixed-signal circuits

CHAIRS

Marcin Kowalczyk, AGH University of Krakow
Camille Monière, Université Bretagne Sud – Lab-STICC UMR 6285

STEERING COMMITTEE

Alfonso Rodríguez, Universidad Politécnica de Madrid, Madrid, Spain
Diana Goehringer, TU Dresden
Jean-Pierre David, Ecole Polytechnique de Montreal
Joao M. P. Cardoso, University of Porto
Marek Gorgon, AGH University of Science and Technology
Miguel Chavarrías, Universidad Politécnica de Madrid, Madrid, Spain
Michael Huebner, Brandenburg University of Technology
Tomasz Kryjak, AGH University of Science and Technology
Paolo Meloni, University of Cagliari
Sergio Pertuz, TU Dresden, Dresden, Germany
Sebastien Pillement, University of Nantes – IETR