CALL FOR PARTICIPATION
The 1st IEEE International Conference on LLM-Aided Design (LAD)
June 26-27, 2025 | Stanford University, Stanford, CA, USA
==> Early Registration Deadline extended to June 15th. https://iclad.ai/registration
Keynote Speakers:
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Christopher Manning, Stanford
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Jeff Dean, Google DeepMind and Google Research
Invited Speakers:
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Ruchir Puri, IBM
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Karina Nguyen, OpenAI
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Nathaniel Pinckney, NVIDIA
Sponsors: AMD, Cadence, ChipAgents, Cognichip, Google, Intel, IBM, Mediatek, NVIDIA, NXP, Qualcomm, Si2, Siemens, Synopsys, Turing, TSMC, IEEE CEDA, IEEE, IEEE Solid-State Circuits Society
The 2025 IEEE International Conference on LLM-Aided Design will focus on how to use LLM (Large Language Model) as a methodology to help design circuits, software, and computing systems with improved quality, productivity, robustness, and cost. It is the first of its kind international conference in the community that will focus on discussing results that leverage the significant advancement and innovation captured by the generative AI and LLM technology to offer new methods and solutions for design automation, software development, among other fields, targeting various existing and emerging applications. The conference will be a timely venue that will host leading researchers and thought leaders in this fast-growing area and will provide a forum for researchers and practitioners to present their latest results, contribute open-source LLM models and relevant solutions, datasets, tool flows, and offer benchmarking, testing and validation methods.
Venue: Paul Brest Hall, Stanford University
As part of ICLAD, we invite you to participate in the ICLAD-DAC 2025 Hackathon (https://iclad.ai/genai-chip-hackathon)
Date & Location: June 22, Moscone West, San Francisco (co-located with DAC)
The ICLAD-DAC 2025 Hackathon is a competitive research, and educational event where participants will use language models to solve specified chip design problems across the RTL to GDSII flow (e.g. RTL debugging and physical design). The hackathon aims to evaluate how effectively language models can assist in real-world chip design challenges by assigning tasks of varying difficulty for completion.




June 10th, 2025
Daniela Lopez de Luise
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